Hardware Acceleration Engineer

We are seeking an experienced Hardware Acceleration Engineer with 7+ years of experience designing and building high‑performance, low‑latency hardware systems that accelerate critical network infrastructure and trading system components. You will work on cutting‑edge FPGA designs, collaborating closely with traders, software engineers, and infrastructure teams to deliver production‑grade solutions that interface seamlessly with modern server platforms.

Responsibilities

• Design, implement, test, and verify FPGA and/or ASIC solutions for low‑latency, high‑throughput systems
• Develop RTL using VHDL, Verilog, or SystemVerilog, alongside C/C++ for control, integration, and tooling
• Perform RTL synthesis and write timing, area, and performance constraints
• Build digital simulations and self‑checking testbenches to ensure correctness and robustness
• Research and prototype new low‑latency techniques, platforms, and architectures, identifying opportunities for integration into production trading systems
• Support post‑silicon bring‑up, debugging, and validation in lab and production environments
• Leverage best‑in‑class commercial hardware or design in‑house solutions to ensure compatibility with cutting‑edge server and networking technology
• Work in a multidisciplinary environment alongside traders, software developers, and infrastructure engineers

Required Experience

• 6+ years of professional experience designing, coding, testing, and verifying FPGA and/or ASIC systems
• Strong proficiency in VHDL, Verilog, or SystemVerilog, with working knowledge of C or C++
• Experience with RTL synthesis, timing closure, and writing area and performance constraints
• Experience with digital simulators and self‑checking testbenches
• Solid understanding of hardware design trade‑offs, including pipelining, resource utilization, latency optimization, and fixed‑point arithmetic
• Proficiency in Python, C++, or similar languages for tooling, testing, simulation, and automation

Preferred Experience

• Hands‑on experience working with latest‑generation Xilinx FPGA platforms
• Experience designing and building custom IP cores for performance‑critical systems
• Experience accelerating machine learning workloads on FPGAs or custom ASICs
• Understanding of ML fundamentals (neural networks, inference optimization, quantization) and familiarity with frameworks such as PyTorch or TensorFlow
• Experience with HLS or ML‑to‑hardware frameworks such as hls4ml, FINN, or Vitis AI
• Experience with ML compiler and lowering infrastructures such as MLIR, TVM, XLA, or similar toolchains for mapping, optimizing, and deploying machine learning models onto FPGA, ASIC, or accelerator targets
• Background in latency‑critical and resource‑constrained ML systems, including real‑time inference, high‑frequency trading infrastructure, signal processing pipelines, or comparable performance‑sensitive domains
  Familiarity with hardware‑centric functional verification methodologies-including SystemVerilog‑based verification, UVM, or Python‑driven frameworks to validate ML accelerators and data‑path correctness